1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly to a semiconductor storage device having a peripheral circuit region and a memory cell region.
2. Description of the Related Art
A semiconductor storage device represented by a DRAM (Dynamic Random Access Memory) includes, in general, a memory cell region in which information is stored and a peripheral circuit region that controls writing information to the memory cell region and reading it therefrom.
In recent years, in such a semiconductor storage device, there is a growing demand for an increase in storage capacity. For this purpose, the semiconductor storage device is reduced in size and microminiaturized. However, the reduction in size and the microminiaturization reduces the distance between wiring lines, leading to an increase in parasitic capacitance between wiring lines and therefore to signal delay.
To solve the problem of the signal delay, for example, JP 2001-156267 and JP 2002-343862 disclose a method of forming a cavity in a space between electrodes and between wiring layers for the purpose of reducing the parasitic capacitance between wiring lines.
The aforementioned method is intended to reduce the parasitic capacitance between wiring lines, such as gate electrodes (word lines) and contact plugs, in the memory cell region. However, it gives no consideration to other wiring layers, particularly in the peripheral circuit region. In other words, no solution is presented for the problem of the signal delay due to the wiring layers in the peripheral circuit region. Therefore, also for the wiring layer in the peripheral circuit region, the requirement is to reduce the parasitic capacitance between wiring lines.